A Multi-Core/Multi-Chip Scalable Architecture of Associative Processors Employing Bell-Shaped Analog Matching Cells

摘要：

A methodology for building a low-power high-capacity associative system has been developed. In the system,matching cells having bell-shaped I-V characteristics play the role of similarity-evaluation elements and can be replaced by nanoscale quantum-effect devices. The study is aiming to extend the current CMOS designs to the coming era of nano-devices. A multi-core/ multi-chip architecture has been developed in a 0.18μm standard CMOS technology. The system is scalable to adapt to the vast-scale integration capacity provided by nanoscale devices. Solutions to the problems of device characteristics variability and signal propagation delay in inter-chip interconnects have been developed in the study.

作者: Trong Tu Bui Tadashi Shibata

作者单位: Department of Frontier Informatics The University of Tokyo,5-1-5 Kashiwanoha,Kashiwa-shi,Chiba,277-8 Department of Electrical Engineering and Information Systems The University of Tokyo,5-1-5 Kashiwano

会议类型: 国际会议

会议名称: 9th International Conference on Solid-State and Integrated-Circuit Technology(第9届固态和集成电路国际会议)

会议地点: 北京

会议语种:英文

页码: 1819-1822

在线出版日期: 2008-10-20（万方平台首次上网日期，不代表论文的发表时间）