Analog/RF Design Techniques for High Performance Nanoelectronic On-Chip Interconnects

摘要：

On-chip interconnects form the bottleneck of VLSI system performance. As technology progresses,VLSI on-chip interconnects encounter increasingly significant challenges,such as (1) signal attenuation and (2) crosstalk coupling. This paper proposes two analog/RF design techniques for high performance nanoelectronic on-chip interconnects: (1) application of distributed amplifiers for signal attenuation compensation by reducing interconnect effective resistance,and (2) application of bandpass filters for noise immunity in a frequency separated VLSI on-chip communication system. HSPICE-RF simulation results in 65nm CMOS technology verify that the proposed analog/RF design techniques achieve improved performance and reliability for high performance nanoelectronic on-chip interconnects.

作者: Bao Liu

作者单位: Electrical and Computer Engineering Department Unversity of Texas,San Antonio,TX 78249

会议类型: 国际会议

会议名称: 9th International Conference on Solid-State and Integrated-Circuit Technology(第9届固态和集成电路国际会议)

会议地点: 北京

会议语种:英文

页码: 1831-1834

在线出版日期: 2008-10-20（万方平台首次上网日期，不代表论文的发表时间）