A Core-based Multi-function Security Processor with GALS Wrapper

摘要：

The security processor proposed In this paper is composed by multiple cryptographic cores. And due to the use of embedded DMA and data burst transfer,the processor can act as a bus master. This architecture improves the efficiency of system bus and reduces the burden of host CPU. Additionally,the proposed processor is connected to the system bus via a GALS Wrapper. Thus,high throughput can be achieved by using faster clock than the host CPU utilizes. On the other hand,the clock of the security processor can also be slowed down if the low power application is desired.

作者: Dan Cao Jun Han Xiao-yang Zeng Shi-ting Lu

作者单位: State-Key Lab of ASIC and System,Fudan University,Shanghai 201203,China

会议类型: 国际会议

会议名称: 9th International Conference on Solid-State and Integrated-Circuit Technology(第9届固态和集成电路国际会议)

会议地点: 北京

会议语种:英文

页码: 1839-1842

在线出版日期: 2008-10-20（万方平台首次上网日期，不代表论文的发表时间）