Design and Implementation of a High-performance 64-bit Floating-point Reciprocal and Square Root Reciprocal Unit

摘要：

This paper designs a 64-bit floating-point reciprocal and square root reciprocal unit of a stream processor (FT64),which combines the methods of table look-up and functional iteration to implement division and square root operations. This unit which is implemented with two pipeline stages provides the initial value for the iteration of division and square root. A semi-custom and full-custom mixed design method is adopted to improve its performance,and a mixed verification method is also proposed to verify the unit. The results of verification show that the unit can achieve the performance of 1 GHz under the typical condition of 0.13μm CMOS technology.

作者: Chaochao Feng Shaoqing Li Minxuan Zhang

作者单位: National Laboratory for Paralleling and Distributed Processing,School of Computer,National University of Defense Technology,Changsha,Hunan 410073,P.R.China

会议类型: 国际会议

会议名称: 9th International Conference on Solid-State and Integrated-Circuit Technology(第9届固态和集成电路国际会议)

会议地点: 北京

会议语种:英文

页码: 1851-1854

在线出版日期: 2008-10-20（万方平台首次上网日期，不代表论文的发表时间）