A Dual-ported Variable-way L1 D-cache Design for High Performance Embedded DSP

摘要：

This paper proposes a truly dual-ported variable-way set-associative L1 D-cache design for high performance embedded DSP (Digital Signal Processor). Several power-efficient D-cache optimizations are implemented in the design,which try to reduce the energy consumption of the L1 D-cache without affecting the performance significantly. The strategy to verify the L1 D-cache controller is also presented in this paper,which complements the simulation approach with the formal method by using System Verilog assertions. Experimental results show that miss rate of the L1 D-cache is about 5% better than that of a single-ported one due to dual-ported references. And,the miss penalty is improved by more than 20% compared with a baseline L1 D-cache without these optimizations.

作者: Di Jia Hu He Yihe Sun

作者单位: Institute of Microelectronics,Tsinghua University,Tsinghua National Laboratory of Information and Technology,Beijing 100084,P.R.China

会议类型: 国际会议

会议名称: 9th International Conference on Solid-State and Integrated-Circuit Technology(第9届固态和集成电路国际会议)

会议地点: 北京

会议语种:英文

页码: 1855-1858

在线出版日期: 2008-10-20（万方平台首次上网日期，不代表论文的发表时间）