A Compact Direct Digital Frequency Synthesizer for System-on-chip

摘要：

A compact direct digital frequency synthesizer (DDFS) for system-on-chip (SoC) is developed in this paper. For smaller chip size and lower power consumption,the phase to sine mapping data is compressed by using sine symmetry technique,sine-phase difference technique,quad line approximation (QLA) technique and quantization and error read only memory (QE-ROM) technique. The ROM size is reduced by 98 % using the techniques mentioned above. A compact DDFS chip with 32-bit phase storage depth and a 10-bit on-chip digital to analog converter(DAC) has been successfully implemented using standard 0.35um CMOS process. The core area of the DDFS is 1.6mm2. It consumes 167 mW at 3.3V,and its spurious free dynamic range (SFDR) is 61dB.

作者: Cao Xiaodong Ni Weining Yuan Ling Hao Zhikun Shi Yin

作者单位: Institute of Semiconductors,Chinese Academy of Sciences,Beijing 100083,P.R.China

会议类型: 国际会议

会议名称: 9th International Conference on Solid-State and Integrated-Circuit Technology(第9届固态和集成电路国际会议)

会议地点: 北京

会议语种:英文

页码: 1863-1866

在线出版日期: 2008-10-20（万方平台首次上网日期，不代表论文的发表时间）