A Novel DCPLL with Small-area and Low-power DCO for SoC Applications

摘要：

This paper presents a novel digitally controlled phase-locked loop (DCPLL) for SoC applications. The DCO of the DCPLL is designed by a flexible design method. By the method,a high performance of DCO can be implemented in a straightforward way. Finally,the DCPLL design is implemented by SMC 0.18 μm logic 1P6M CMOS technology. The area of the DCPLL is 0.08mm2. The post-layout simulation results by Spice show that the frequency range of the digitally controlled oscillator (DCO) is from 96 MHz to 542.5 MHz and the resolution of the DCO is about 22 ps. The power consumption of the DCPLL is 6.14 mW when the DCO operates at 400 MHz.

作者: Chen Juan Fang Shou-hai Chen Xin

作者单位: College of Information Science and Engineering,Nanjing University of Technology,Nanjing 210009,China National ASIC System Engineering Research Center,Southeast University,Nanjing 210096,China

会议类型: 国际会议

会议名称: 9th International Conference on Solid-State and Integrated-Circuit Technology(第9届固态和集成电路国际会议)

会议地点: 北京

会议语种:英文

页码: 1867-1870

在线出版日期: 2008-10-20（万方平台首次上网日期，不代表论文的发表时间）