The Implementation of 1-GHz Bit-Stream Adder used in Signal Processing in a 0.18-μm CMOS Technology

摘要：

A kind of arithmetic and its implementation of bit-stream adder which can be used in digital signal processing were discussed in this paper. Compared with multi-bit adder,the bit-stream adder has the advantages of much simple structure and much small routing area. The ideal circuit model of the bit-stream adder was improved with a pipe line structure to make it work correctly in high frequency range. In order to increase the operating frequency,the physical circuit was deigned with the source coupled logic (SCL) technology. The IC was fabricated with TSMCs 0.18-μm CMOS process. The chip area is 475μm×570 μm. The experimental results show that the function of the chip matches the demand of design and the chip can work at a frequency of higher than 1 GHz.

作者: Yong Liang Qiao Meng Zhi-Gong Wang

作者单位: Institute of RF-& OE-ICs,Southeast University,Nanjing 210096,P R.China

会议类型: 国际会议

会议名称: 9th International Conference on Solid-State and Integrated-Circuit Technology(第9届固态和集成电路国际会议)

会议地点: 北京

会议语种:英文

页码: 1871-1873

在线出版日期: 2008-10-20（万方平台首次上网日期，不代表论文的发表时间）