A CMOS Quaternary-to-Binary Logic Decoder

摘要：

This paper proposes a quatemary-to-binary logic decoder using current-mode multiple-valued logic (MVL) CMOS circuits. The circuit is achieved a device reduction of 23.5%,an interconnection reduction of 25.0%,and a power-delay-product reduction of 43.1%. Therefore,this circuit is superior to the previous circuit in both the circuit occupied area and the reliability. The validity and effectiveness of the proposed circuits are verified through the HSPICE under Hynix 0.25um standard CMOS technology with the supply voltage 2.5 V.

作者: Jeong Beom Kim

作者单位: Dept.of Electronics Eng.,Kangwon National University,R.of Korea

会议类型: 国际会议

会议名称: 9th International Conference on Solid-State and Integrated-Circuit Technology(第9届固态和集成电路国际会议)

会议地点: 北京

会议语种:英文

页码: 1874-1876

在线出版日期: 2008-10-20（万方平台首次上网日期，不代表论文的发表时间）