A New High Compression Compressor for Large Multiplier

摘要：

A new high compression compressor is proposed in this paper. This compressor has 7 inputs,2 output,2 carry-ins from adjacent two cells and 2 carry-outs to the next two cells. It achieves higher compression ratio than 4:2 compressor,5:2 compressor and 6:2 compressor. Simulation shows that a 64×64 bit multiplier using this proposed 7:2 compressor is not only 16% faster than multiplier built with 3:2 compressors,but also outperforms multiplier built with other commonly used compressors.

作者: Weinan Ma Shuguo Li

作者单位: Institute of Microelectronics,Tsinghua University,Beijing 100084,P.R.China

会议类型: 国际会议

会议名称: 9th International Conference on Solid-State and Integrated-Circuit Technology(第9届固态和集成电路国际会议)

会议地点: 北京

会议语种:英文

页码: 1877-1880

在线出版日期: 2008-10-20（万方平台首次上网日期，不代表论文的发表时间）