Integrate Custom Layout with ASIC Back-end Design Flow for High Performance Datapath Design

摘要：

A method to integrate custom layout with ASIC back-end flow for high performance datapath design is introduced in this paper. It combines custom physical design techniques with conventional standard-cell based timing-driven back-end design flow. The results of two subchip design cases using this method for datapath circuits and implemented based on Fujitsu 90nm process are presented,achieving advantages such as high area utilization,good speed,and low power consumption while ensuring timing continuous convergence.

作者: Wei Wang Marwan Ashkar Yanke Gu Ligang Hou Wuchen Wu

作者单位: VLSI & System Laboratory,Beijing University of Technology,Beijing 100022,PR.China C2 Microsystems Inc.,Beijing 100080,P.R.China C2 Microsystems Inc.,Beijing100080,P.R.China

会议类型: 国际会议

会议名称: 9th International Conference on Solid-State and Integrated-Circuit Technology(第9届固态和集成电路国际会议)

会议地点: 北京

会议语种:英文

页码: 1901-1904

在线出版日期: 2008-10-20（万方平台首次上网日期，不代表论文的发表时间）