High Speed CMOS Output Stage for Integrated DC-DC Converters

摘要：

A Hybrid Waffle layout technique is introduced for the design of CMOS power transistors in integrated low voltage DC-DC converters. Comparing with conventional Multi-Finger layout scheme,the Hybrid Waffle layout scheme allows optimized trade-off between device on-resistance and metal interconnect resistance to minimize overall on-resistance. Interestingly,the reduced channel width per unit area also leads to lower gate capacitance and faster switching speed. This paper presents a prototype DC-DC converter IC that contains integrated gate drivers,protection circuits and CMOS output transistors. Implemented in a standard 0.25μm CMOS,this IC can be switched at 12.5MHz with output current rated at 800mA with input voltage of up to 4.2V. Peak power efficiency of 85% was observed at 100mA. Die size is 1.1×1.5 mm2.

作者: Wai Tung Ng Marian Chang Abraham Yoo Jiri Langer Tim Hedquist Helmut Schweiss

作者单位: Electrical and Computer Engineering,University of Toronto,Toronto,ON Canada M5S 3G4 Materials Science and Engineering,University of Toronto,Toronto,ON Canada M5S 3E4 On Semiconductor Inc.,5005 East McDowell Road,Phoenix,AZ 85008

会议类型: 国际会议

会议名称: 9th International Conference on Solid-State and Integrated-Circuit Technology(第9届固态和集成电路国际会议)

会议地点: 北京

会议语种:英文

页码: 1909-1912

在线出版日期: 2008-10-20（万方平台首次上网日期，不代表论文的发表时间）