A Low Power SHA-less Pipelined ADC used in DVB-S2

摘要：

A 8-b 125MS/s pipelined Analog-to-Digital Converter (ADC) used in DVB-S2 is presented in this paper. Based on reviewing low-power design techniques of high speed ADCs,several technologies are used in the design including the SHA-less architecture to reduce the power dissipation significantly. Detailed analysis is given about the relationship between the closed loop bandwidth (BWclose and the current of operational amplifier (OPAMP) used in Multiply Digital-to-Analog Converter (MDAC) to get the lowest power dissipation which can satisfy the ADC. The ADC is realized in SMIC 0.18um 1P6M CMOS process and according to the simulation results,the SNDR is 48dB with the power of 23.5mW.

作者: Zhang Zhang Xiaoyang Zeng Jian Li Lei Xie Yawei Guo

作者单位: State Key Lab of ASIC & System,Fudan University,Shanghai,201203,P R.China Comlent Technology Inc.,Shanghai 201203,P.R China

会议类型: 国际会议

会议名称: 9th International Conference on Solid-State and Integrated-Circuit Technology(第9届固态和集成电路国际会议)

会议地点: 北京

会议语种:英文

页码: 1913-1916

在线出版日期: 2008-10-20（万方平台首次上网日期，不代表论文的发表时间）