CMOS Folding and Interpolating ADC with a Mized-Averaging Distributed T/H Circuit

摘要：

An 8-bit 200MHz low-power CMOS folding and interpolating analog-to-digital converter is presented. A novel mixed-averaging distributed T/H circuit is proposed to decrease the nonlinearity error of the ADC. The DNL/INL is 0.3/0.2LSB according to MATLAB simulation results. This ADC is implemented in 0.5um CMOS technology and the total power dissipation is merely 96mW at a sampling rate of 200MHz.

作者: Zhen Liu Song Jia Yuan Wang Lijiu Ji Xing Zhang

作者单位: Key Laboratory of Microelectronic Devices and Circuits,Institute of Microelectronics,Peking Universi Key Laboratory of Microelectronic Devices and Circuits,Institute of Microelectronics,PekingUniversit

会议类型: 国际会议

会议名称: 9th International Conference on Solid-State and Integrated-Circuit Technology(第9届固态和集成电路国际会议)

会议地点: 北京

会议语种:英文

页码: 1921-1924

在线出版日期: 2008-10-20（万方平台首次上网日期，不代表论文的发表时间）