An 8-bit 700Ms/s Current-steering DAC

摘要：

This paper is concerned with the design of a high speed current steering DAC. Techniques to improve static precision are preserved while their negative influences on dynamic performance are suppressed. The prototype is implemented with the SMIC 0.13μm process. With an update rate of 700Msamples/s,measurements show that the DAC achieves over 40dB SFDR under a sampling rate of 700Ms/s and consumes l0mW (8.4mW for Analog) with 1.2V voltage supply.

作者: Lei Luo Jun Yan Ren

作者单位: ASIC & Systems State Key Laboratory,Fudan University Shanghai 201203 China

会议类型: 国际会议

会议名称: 9th International Conference on Solid-State and Integrated-Circuit Technology(第9届固态和集成电路国际会议)

会议地点: 北京

会议语种:英文

页码: 1925-1928

在线出版日期: 2008-10-20（万方平台首次上网日期，不代表论文的发表时间）