A 10MHz to 600MHz Low Jitter CMOS PLL for Clock Multiplication

摘要：

This paper describes a phase-locked loop (PLL) designed for clock multiplication. The PLL has a locking range from 10MHz to 600MHz at 1.8V power supply. It has a very low peak-to-peak jitter which less than 50ps at 150MHz output frequency. It has been fabricated in a 0.18μm CMOS process. The area of the active layout of the PLL is 560um*400μm,and power consumption is about 6mW.

关键词： PLL VCO clock jitter

作者: Bing Fan Luo-sheng Li Zi-qiao Chu Dong-hui Wang Chao-huan Hou

作者单位: Institute of Acoustics,Chinese Academy of Sciences,Beijing 100190,P.R.China Digital Media R&D Center,Samsung Electronics Co.,LTD.Korea

会议类型: 国际会议

会议名称: 9th International Conference on Solid-State and Integrated-Circuit Technology(第9届固态和集成电路国际会议)

会议地点: 北京

会议语种:英文

页码: 1929-1932

在线出版日期: 2008-10-20（万方平台首次上网日期，不代表论文的发表时间）