Design of 8-bit 250MHz sample-hold circuit

摘要：

A 0.35um BiCMOS dual-path,dual-differential sample-and-hold circuit is presented in this paper. The resolution of the circuit reaches 8 bits,and the sampling rate reaches 250MSPS. The circuit features an alternate working mode,and reduces the circuit demand for speed. From simulation of the circuit,it can be found that SNR is 55.8dB,that TNL and DNL are smaller than that of 8-bit ADC,which is ±0.2LSB,and that the power current is 28mA if the sampling rate is 250MSPS at an input signal of 1 Vp-p with power supply of 3.3V The sample test results are as follows. SNR is 47.6dB. INL and DNL are lower than that of 8 bit ADC,which is ±0.8LSB.

关键词： Sample-and-Hold Dual-path Linearity SNR dual-differential

作者: Kunguang Xiao Yonglu Wang Shutao Zhou Weidong Yang

作者单位: National Labs of Analog ICs,Chongqing 400060,P.R.China Sichuan Institute of Solid-state Circuit,CETC Sichuan Institute of Solid-state Circuit,CETC,Chongqing 400060,P.R.China

会议类型: 国际会议

会议名称: 9th International Conference on Solid-State and Integrated-Circuit Technology(第9届固态和集成电路国际会议)

会议地点: 北京

会议语种:英文

页码: 1953-1956

在线出版日期: 2008-10-20（万方平台首次上网日期，不代表论文的发表时间）