A Novel 1.25GSPS Ultra High-Speed Comparator in 0.18μm CMOS

摘要：

Based on the preamplifier-latch theory,a new topology structure of ultra high-speed comparator with low offset voltage applied to ultra high-speed A/D converters,which is composed of a preamplifier that includes a positive and negative resistance connected in parallel as its load,a regenerative latch and a simple output stage,is proposed. The method to analyze the speed and input offset voltage of the circuit is described Based on SMC 0.18um/1.8V mixed-signal CMOS process,the proposed comparator is designed and simulated by Cadence Spectre. Simulation results show that the circuit can work under as high a clock frequency as 1.25GHz and its maximum offset voltage is 0.6mV With 1.0V input swing,the circuit can be used to realize 10-bit resolution.

作者: Bao-ni Han Yin-tang Yang Zhang-ming Zhu

作者单位: Institute of Microelectronics,Xidian University,Xian 710071,China

会议类型: 国际会议

会议名称: 9th International Conference on Solid-State and Integrated-Circuit Technology(第9届固态和集成电路国际会议)

会议地点: 北京

会议语种:英文

页码: 1957-1960

在线出版日期: 2008-10-20（万方平台首次上网日期，不代表论文的发表时间）