A Cost-Efficient 12-Bit 20Msamples/s Pipelined ADC
A 12-bit 20MS/s cost-efficient pipelined analog-digital converter is presented. A dedicated first stage is proposed to eliminate the need of front-end SHA. Passive capacitor error-averaging technique (PCEA) and opamp sharing scheme are employed to achieve high resolutions and low power and area. The offset and 1/f noise of Opamp is reduced by interchanging the polarity of input and output of Opamp during different clock; phases. Simulated with 0.5um CMOS technology,the ADC dissipates 65mw from a 5V supply,and achieves a peak SNDR of 70.1dB with a 1MHz full-scale sine input at 20MS/s.
Cao Junmin Chen Zhongjian Lu Wengao Zhao Baoying
Key Laboratory of Microelectronic Devices and Circuits,Institute of Microelectronics,Peking University,100871,P.R.China
国际会议
9th International Conference on Solid-State and Integrated-Circuit Technology(第9届固态和集成电路国际会议)
北京
英文
1961-1964
2008-10-20（万方平台首次上网日期，不代表论文的发表时间）