Low Power Folding/Interpolating ADC with a Novel Dynamic Encoder Based on ROM Theory

摘要：

A 6-bit 200Msps Folding/Interpolating analog to digital converter (ADC) with a novel dynamic encoder based on Rom theory is presented. The Precharge & Evaluate dynamic circuit is employed in the novel encoder and the bit synchronization logic to achieve high speed and reduce power dissipation. Realized in SMIC 0.35um digital CMOS process,the whole ADC consumes only 35mW at a 3.3V voltage supply.

作者: Jilei Yin Yuan Wang Song Jia Zhen Liu

作者单位: Key Laboratory of Microelectronic Devices and Circuits,Institute of Microelectronics,Peking University,100871

会议类型: 国际会议

会议名称: 9th International Conference on Solid-State and Integrated-Circuit Technology(第9届固态和集成电路国际会议)

会议地点: 北京

会议语种:英文

页码: 1969-1972

在线出版日期: 2008-10-20（万方平台首次上网日期，不代表论文的发表时间）