A Study of a10-bit 50MS/s Low Voltage Low Power Pipelined ADC

摘要：

In this paper,a 10-bit 50-MS/s analog-to-digital converter (ADC) is presented. A power consumption of 10.6 mW is designed by using low power gain-boosted OP-Amp and dynamic comparator. Bootstrapped switch achieves rail-to-rail signal swing at low-voltage power supply. This circuit is designed in aSMIC 1.2-V 0.13-um CMOS technology. The results show that the proposed Nyquist rate ADC provides a potential solution for low-power high-speed applications,e.g.,DVB-H,DVB-T and WLANs.

作者: Cuncai Zhang Hui Wang Yuhua Cheng

作者单位: Shanghai Research Institute of Microelectronics (SHRIME),Peking University 608 Shengxia Road,Zhang-J Shanghai Research Institute of Microelectronics (SHRIME),Peking University 608 Shengxia Road,Zhang-J

会议类型: 国际会议

会议名称: 9th International Conference on Solid-State and Integrated-Circuit Technology(第9届固态和集成电路国际会议)

会议地点: 北京

会议语种:英文

页码: 1980-1983

在线出版日期: 2008-10-20（万方平台首次上网日期，不代表论文的发表时间）