A Fast-Locking Phase-Locked Loop Using a Seven-State Phase Frequency Detector
A seven-state phase frequency detector (S.S PFD) is proposed for fast-locking charge pump based phase-locked loops (CPPLLs) in this paper. The locking time of the PLL can be significantly reduced by using the seven-state PFD to inject more current into the loop filter. In this stage,the bandwidth of the PLL is increased or decreased to track the phase difference of the reference signal and the feedback signal. The proposed architecture is realized in a standard 0.35μm 2P4M CMOS process with a 3.3V supply voltage. The locking time of the proposed PLL is 1.102μs compared with the 2.347μs of the PLL based on continuous-time PFD and the 3.298μs of the PLL based on the pass-transistor tri-state PFD. There are 53.05% and 66.59% reductions of the locking time. The simulation results and the comparison with other PLLs demonstrate that the proposed seven-state PFD is effective to reduce locking time.
Silin Liu Zhikun Hao Heping ma Ling Yuan Yin Shi
Institute of Semiconductor,Chinese Academy of Sciences,Beijing,100083,P.R.China
国际会议
9th International Conference on Solid-State and Integrated-Circuit Technology(第9届固态和集成电路国际会议)
北京
英文
2004-2007
2008-10-20（万方平台首次上网日期，不代表论文的发表时间）