Process-Design Co-Optimization for FPGA

摘要：

Advancement of field programmable gate array (FPGA) faces many challenges. Among the major ones are power management and high speed transceiver I/O demands. To overcome the challenges,process-design co-optimization is required,With co-optimization of process,circuit,and architecture,45% static power reduction is achieved for a 40nm FPGA design. With optimized analog devices,high data rate (8.5Gbps) transceivers are produced using a 40nm digital process.

作者: Qi Xiang

作者单位: Altera Corporation,101 Innovation Drive,San Jose,CA 95134

会议类型: 国际会议

会议名称: 9th International Conference on Solid-State and Integrated-Circuit Technology(第9届固态和集成电路国际会议)

会议地点: 北京

会议语种:英文

页码: 2039-2042

在线出版日期: 2008-10-20（万方平台首次上网日期，不代表论文的发表时间）