A Fully Digital DLLs Integrated in FPGAs

摘要：

This paper presents fully digital dedicated on-chip DLLs,allowing for synchronization of external and internal clocks in FPGAs. DLL clock delay compensation circuit,digital clock phase shifter,digital duty-cycle-correction circuit and clock divider. In a Smic 0.18um CMOS process,its operation frequency range is 25MHz～300MHz at 1.8V. The peak-to-peak jitter is 35ps. Dueing to the digital architecture of the DLL,it only need a single synchronization step when the frequency of the input clock signal is stable. DLLs locking time is 13 clock cycles. In addition to providing zero delay with respect to a user source clock,the DLL can provide three phase-shifted version of the source clock. The DLL can also divide the user source clock by up to 16. The values allowed for this property are 1.5,2,2.5,3,4,5,8,or 16; the default value is 2.

关键词： Clock delay Delay-Locked Loop phase shifter FPGA

作者: WenYu Jin-mei Lai

作者单位: State Key Lab of ASIC & Systems,Dept.Microelectronics,Fudan University,Shanghai,200433,P.R.China

会议类型: 国际会议

会议名称: 9th International Conference on Solid-State and Integrated-Circuit Technology(第9届固态和集成电路国际会议)

会议地点: 北京

会议语种:英文

页码: 2051-2053

在线出版日期: 2008-10-20（万方平台首次上网日期，不代表论文的发表时间）