A Low Power Dynamic Pseudo Random Bit Generator for Test Pattern Generation

摘要：

Pseudo random bit generator is widely used in BIST for test pattern generation. Typical pseudo random bit generator adopts linear feedback shift register (LFSR) as its basic circuit. Dynamic LFSR (DLFSR) which has better cryptographic properties with respect to typical LFSR consumes more power. This paper forwards a low power DLFSR (LDLFSR) circuit which achieves comparable performance with less power consumption. Typical LFSR,a DFLSR,a LDLFSR are compared on randomness property and inviolability property. Multi-layer perceptron neural networks are used to test these LFSRs inviolability property. Result shows that LDLFSR keeps comparable performance with a 7% power reduction and a 5.6% area reduction.

作者: Li-gang Hou Xiao-hong Peng Wu-chen Wu

作者单位: VLSI & System Lab,Beijing University of Technology,Beijing 100022,P.R.China

会议类型: 国际会议

会议名称: 9th International Conference on Solid-State and Integrated-Circuit Technology(第9届固态和集成电路国际会议)

会议地点: 北京

会议语种:英文

页码: 2079-2082

在线出版日期: 2008-10-20（万方平台首次上网日期，不代表论文的发表时间）