A New Configuration Scheme for Delay Test in Non-simple LUT FPGA Designs
With the increased use of FPGA in widespread applications,its size and speed has been rapidly increased,so more and more problems associated with performance defects are emerging. Performance defects such as delay defects will not lead to a functional fault,but will limit the frequency of the system. Only Stuck-at testing has not been sufficient to guarantee the reliability and quality,so testing delay fault becomes necessary. In this paper,in order to improve the efficiency and coverage of delay test,we first select the most suitable delay fault model for FPGAs,which is a good simulation for the actual situation. At the same time we proposed a new configuration on the basis of this. This method takes full advantage of the FPGAs reconfiguration feature. It not only omits complex test pattern generation,but also optimizes the BIST circuits to minimize the area cost,and reaches higher fault coverage. To verify the theory,we use Xilinx vertex4 devices on the experimental test,and achieved approving results.
FPGA configuration delay-test LUT MUX
Botao Sun Jianhua Feng Teng Lin
Key Laboratory of Microelectronic Devices and Circuits,Institute of Microelectronics,Peking University,100871,P.R.China
国际会议
9th International Conference on Solid-State and Integrated-Circuit Technology(第9届固态和集成电路国际会议)
北京
英文
2083-2086
2008-10-20（万方平台首次上网日期，不代表论文的发表时间）