A Novel Linear Histogram BIST for ADC

摘要：

This paper proposes a novel histogram BIST scheme for ADC static testing. For a monotonic ADC,the out codes have an approximate stair-like proportional relationship to the input signal. Based on this property,a space decomposition technique is proposed to reduce the testing time. By utilizing this technique,ADCs static parameters can be estimated in shorter testing time with low hardware overhead. The availability of proposed histogram BIST scheme has been verified by simulation and the test results have been compared with those obtained from Vengy SOC 93000.

作者: Jianguo Ren Jianhua Feng Hongfei Ye

作者单位: Key Laboratory of Microelectronic Devices and Circuits,Institute of Microelectronics,Peking University,100871

会议类型: 国际会议

会议名称: 9th International Conference on Solid-State and Integrated-Circuit Technology(第9届固态和集成电路国际会议)

会议地点: 北京

会议语种:英文

页码: 2099-2102

在线出版日期: 2008-10-20（万方平台首次上网日期，不代表论文的发表时间）