Low-Voltage Limitations and Challenges of Memory-Rich Nano-Scale CMOS LSIs

摘要：

The minimum operating voltage (Vmm) of nano-scale LSIs is investigated,focusing on logic gates,SRAM cells,and DRAM sense amplifiers in LSIs. The Vmin that is governed by SRAM cells rapidly increases as devices are miniaturized due to the ever-larger variation of the threshold voltage (VT) of MOSFETs. The Vmin,however,is reduced to the sub-one-volt region by using repair techniques and new MOSFETs (e.g.,FD-SOIs and/or high-k bulk) that can reduce Vr variations.

作者: Kiyoo Itoh

作者单位: Central Research Laboratory,Hitachi,Ltd.,Kokubunji,Tokyo 185-8601,Japan

会议类型: 国际会议

会议名称: 9th International Conference on Solid-State and Integrated-Circuit Technology(第9届固态和集成电路国际会议)

会议地点: 北京

会议语种:英文

页码: 2111-2114

在线出版日期: 2008-10-20（万方平台首次上网日期，不代表论文的发表时间）