A Reconfigurable Power Efficient Correlator for Channel Estimation in DTMB System

摘要：

This paper presents a power efficient reconflgurable correlator for DTMB channel estimation. In this design,a novel architecture based on Fast Walsh Transform is adopted to perform cyclic correlation. By sharing memory and reusing calculation unit,the proposed reconflgurable architecture supports correlation of PN sequence with code length of 256 and 512 without any increment in hardware cost Based on SMIC 0.18μm standard CMOS technology,the circuit area of presented design is about 41355 gates. The simulation results show that the proposed correlator saves 60% power consumption compared with those of the existed architectures.

作者: Yuan Chen Yun Chen Dan Cao An Pan Xiaoyang Zeng

作者单位: State-Key Lab of ASIC and System,Fudan University,Shanghai 201203,China

会议类型: 国际会议

会议名称: 9th International Conference on Solid-State and Integrated-Circuit Technology(第9届固态和集成电路国际会议)

会议地点: 北京

会议语种:英文

页码: 2124-2127

在线出版日期: 2008-10-20（万方平台首次上网日期，不代表论文的发表时间）