A Method to Lower Power in Speed Negotiation Algorithm of Fiber Channel

摘要：

In this paper,we propose a simple but effective method to reduce the power in the design of the Speed Negotiation Algorithm(SNA). Based on thoroughly analyzing the algorithm and the results of simulation,we identify the large timers,the most commonly used in the SNA,as the most power consuming parts. This paper further develops a partition algorithm to tackle the power issue of the large timers. Utilizing the proposed method,we can reduce the power by 30% as opposed to only 19% if directly applying clock-gating methodology. Combined with clock-gating methodology,we can get 38% reduction in power with no more than 5% increase in area.

作者: Jie Jin Dun Shan Yu Xiao Xin Cui

作者单位: Key Laboratory of Microelectronic Devices and Circuits,Institute of Microelectronics Peking University,Beijing 100871,P.R.China

会议类型: 国际会议

会议名称: 9th International Conference on Solid-State and Integrated-Circuit Technology(第9届固态和集成电路国际会议)

会议地点: 北京

会议语种:英文

页码: 2132-2135

在线出版日期: 2008-10-20（万方平台首次上网日期，不代表论文的发表时间）