A High-speed Low-power Pulse-swallow Divider with Robustness Consideration

摘要：

A high-speed low-power programmable pulse-swallow divider is designed and fabricated in SMIC 0.18-μm CMOS process. Two critical paths that limit the operating frequency are analyzed. The proposed prescaler based on a shift-register-ring is insensitive to the Modulus Control (MC) during its first few input cycles,and thus wrong divide ratio caused by the MCs delay can be avoided. The proposed pulse generator works as a sample/hold block to widen the time slot of the reading process,and thus failure in reading external control words into the swallow counter can also be avoided. A 3.5-GHz integer phase-locked loop (PLL) that uses the divider employing the proposed prescaler and pulse generator provides 21 channels with a 1.2-ppm precision in measurements. The power dissipation is 0.475-mW from a 1.2-V supply under 1.6-GHz operating frequency.

作者: Jie Pan Haigang Yang Li-wu Yang

作者单位: Institute of Electronics,Chinese Academy of Sciences,Beijing 100190,China Graduate University of the Institute of Electronics,Chinese Academy of Sciences,Beijing 100190,China RF Application group,SMC,Shanghai 201203,China

会议类型: 国际会议

会议名称: 9th International Conference on Solid-State and Integrated-Circuit Technology(第9届固态和集成电路国际会议)

会议地点: 北京

会议语种:英文

页码: 2168-2171

在线出版日期: 2008-10-20（万方平台首次上网日期，不代表论文的发表时间）