Low Power and High Performance Zipper Domino Circuits with Charge Recycle Path

摘要：

A charge recycle technique is proposed in this paper to lower the dynamic power and to improve the performance of the zipper domino circuits. Zipper domino circuits of different structures are designed utilizing this technique and simulated based on 65nm,45nm and 32nm BSIM4 SPICE models. The simulation results show that the power-delay product (PDP) is reduced by up to 42.37% as compared to standard domino circuits. Whats more,a power distribution method is introduced in Zipper CMOS full-adder design. Through this method,the charge recycle path is optimized to minimize the power.

作者: Jinhui Wang Na Gong Shuqin Geng Ligang Hou Wuchen Wu Limin Dong

作者单位: VLSI and System Lab,Beijing University of Technology,Beijing 100022,P.R.China College of Electronic and Informational Engineering,Hebei University,Baoding 071002,P R.China

会议类型: 国际会议

会议名称: 9th International Conference on Solid-State and Integrated-Circuit Technology(第9届固态和集成电路国际会议)

会议地点: 北京

会议语种:英文

页码: 2172-2175

在线出版日期: 2008-10-20（万方平台首次上网日期，不代表论文的发表时间）