Heterogeneous Multi-Core SOC Architecture for MPEG Decoding

摘要：

To deal with nowaday multi-standard audio and video processing,a heterogeneous multi-core SOC architecture is presented in this paper,which is composed of a general purpose RISC processor,an audio processing enhanced DSP and dedicated video processing accelerators. To exploit the task level concurrency among audio-video media decoding,an efficiency and flexible HW/SW cooperating architecture is provided for video decoding,a DSP core is integrated for audio decoding individually,and special mechanisms are designed for inner cores communication and data exchange. The proposed architecture is proto-typed on a FPGA system,which can achieve the MPEG-1/2/4 ASP audio-video real-time decoding in the case of 33MHz system frequency.

作者: LIU Feng WANG Chao ZHANG Dong

作者单位: Microprocessor Research & Development Center,Peking University,Beijing,100871 P.R.CHINA

会议类型: 国际会议

会议名称: 9th International Conference on Solid-State and Integrated-Circuit Technology(第9届固态和集成电路国际会议)

会议地点: 北京

会议语种:英文

页码: 2188-2191

在线出版日期: 2008-10-20（万方平台首次上网日期，不代表论文的发表时间）