The Implementation methods of High Speed FIR Filter on FPGA

摘要：

This paper implements a sixteen-order high-speed Finite Impose Response (FIR) filter with four different popular methods: Conventional multiplications and additions,Full custom Distributed Arithmetic (DA) scheme; Add-and-Shift method with advanced calculation schedule. Each scheme is analyzed in detail including implementing process and advantages and/or drawbacks in order to present a practical reference. All of these implementations are aimed to implement on Xilinx Spartan 3 devices and we also compare our results with an industry result produced by Xilinx CoregenTM also using Distributed Arithmetic. The premium add-and-shift method observes up to 80% reduction in total occupied slices and 63.3% versus the largest conventional parallel multiplication implementation.

作者: Ying Li Chungan Peng Dunshan Yu Xing Zhang

作者单位: Key Laboratory of Microelectronic Devices and Circuits,Institute of Microelectronics,Peking University,100871

会议类型: 国际会议

会议名称: 9th International Conference on Solid-State and Integrated-Circuit Technology(第9届固态和集成电路国际会议)

会议地点: 北京

会议语种:英文

页码: 2216-2219

在线出版日期: 2008-10-20（万方平台首次上网日期，不代表论文的发表时间）