Differential Power Analysis and Differential Fault Attack Resistant AES Algorithm and its VLSI Implementation

摘要：

This paper proposes an AES algorithm against both differential power analysis and differential fault analysis and its hardware implementation. This new algorithm emphasizes the feature of defending hardware against two kinds of side-channel attack simultaneously. Since the modified AES algorithm is much more complex than the original one,this paper exploits low hardware cost architecture to realize it Furthermore,a pipelined structure is adopted to achieve high throughput Simulations show that this architecture can protect hardware against both differential power analysis and differential fault attack. Synthesis result demonstrates that this design achieves adequately high data throughput with low hardware cost.

作者: Jia Zhao Jun Han Xiaoyang Zeng Liang Li Yunsong Deng

作者单位: State-Key Lab of ASIC and System,Fudan University Shanghai 201203,China

会议类型: 国际会议

会议名称: 9th International Conference on Solid-State and Integrated-Circuit Technology(第9届固态和集成电路国际会议)

会议地点: 北京

会议语种:英文

页码: 2220-2223

在线出版日期: 2008-10-20（万方平台首次上网日期，不代表论文的发表时间）