Research and Implementation of High-speed Reconfigurable Grain algorithm

摘要：

A high-speed and dynamic reconfigurable hardware architecture of Grain algorithm is presented,which can satisfy the different characteristic of Grain-80 and Grain-128 algorithm. To save the hardware cost and get shorter critical path,we proposed tree network to implement linear and nonlinear feedback function. As to the different high-speed method,this paper perform detailed comparison and analysis. The design has been realized using Alteras FPGA. Synthesis,placement and routing of reconfigurable design have accomplished on 0.18μm CMOS process,the result proves the critical throughput rate can achieve 3.41 Gbps.

作者: Li Wei Dai Zibin Chen Tao Nan Longmei

作者单位: Information Engineering University,Zhengzhou 450004,China

会议类型: 国际会议

会议名称: 9th International Conference on Solid-State and Integrated-Circuit Technology(第9届固态和集成电路国际会议)

会议地点: 北京

会议语种:英文

页码: 2224-2227

在线出版日期: 2008-10-20（万方平台首次上网日期，不代表论文的发表时间）