Layout Prozimity Effects and Device Eztraction in Circuit Designs

摘要：

The scaling of CMOS technology intensifies the interaction between design and process at 45nm or below,causing strong layout-dependent proximity effects. Photolithography,strain silicon engineering,and ion implantation are the primary causes of those effects,whose impacts to design can be mitigated via restrictive design rules and accurate modeling. A novel approach is proposed that seamlessly integrates physical models with geometry processing for device extraction,alleviating the overheads to LVS and circuit simulators in conventional design flow.

作者: Xi-Wei Lin

作者单位: Silicon Engineering Group,Synopsys Inc.,Mountain View,CA,U.S.A.

会议类型: 国际会议

会议名称: 9th International Conference on Solid-State and Integrated-Circuit Technology(第9届固态和集成电路国际会议)

会议地点: 北京

会议语种:英文

页码: 2228-2231

在线出版日期: 2008-10-20（万方平台首次上网日期，不代表论文的发表时间）