A Floorplanning Algorithm For Block Placement In SoC Design

摘要：

With the dramatic increase in size and complexity of systems on chip (SoC),there might be as much as hundreds of macro blocks and millions of standard cells integrated into a single chip. To facilitate signal routing and P/G network construction,one approach is to place macros around the boundary of chip and the remainder is used for arrangement of standard cells. To deal with such kind of placement,we propose an algorithm based on simulated annealing using B*-tree. The proposed algorithm guarantees a feasible solution through perturbation of B*-tree and the experimental results prove it very efficient.

作者: Shanshan Chen Linkai Wang Xiaofang Zhou

作者单位: State Key Laboratory of ASIC and System,Fudan University,Shanghai 201203

会议类型: 国际会议

会议名称: 9th International Conference on Solid-State and Integrated-Circuit Technology(第9届固态和集成电路国际会议)

会议地点: 北京

会议语种:英文

页码: 2268-2271

在线出版日期: 2008-10-20（万方平台首次上网日期，不代表论文的发表时间）