Cluster-based Placement for Multilevel Hierarchical FPGA

摘要：

In this paper,we present a Multilevel Hierarchical FPGA (MFPGA) architecture model and propose a cluster-based placement algorithm for this model. The algorithm has a multi-scale optimized V-shape flow including constructive bottom-up clustering process and top-down placement process. Experimental results indicate that our algorithm improves total wire-length and logic utilization by more than 15% and 10% on average for MCNC benchmark designs compared with the start-of-art vpr tool.

作者: Hui Dai Qiang Zhou Jinian Bian Yanhua Wang

作者单位: Department of Computer Science & Technology,Tsinghua University,Beijing 100084,P.R.China Department of Computer Science & Technology,North China Electric Power University

会议类型: 国际会议

会议名称: 9th International Conference on Solid-State and Integrated-Circuit Technology(第9届固态和集成电路国际会议)

会议地点: 北京

会议语种:英文

页码: 2325-2328

在线出版日期: 2008-10-20（万方平台首次上网日期，不代表论文的发表时间）