A Synthesis Tool for a Tile-Based Heterogeneous FPGA

摘要：

A multi-mode logic cell architecture in a tile-based heterogeneous FPGA is proposed,and a logic synthesis tool,called Vsyn,based on this architecture is presented. The logic cell architecture design and its synthesis tool development are strongly influencing each other. Any feature or parameter from one needs to be fully exercised and verified on the other. In this paper,we presented experimental results based MCNC benchmarks to show that the integration of the synthesis tool and the FPGA architecture can achieve high performance in the targeted FPGA applications. In addition,Vsyn can also target embedded special-purpose macros for the heterogeneous FPGA.

作者: Kun Zhang Hongmin Yu Stanley L.Chen Zhongli Liu

作者单位: Institute of Semiconductors,Chinese Academy of Sciences,Beijing,10083,P.R.China

会议类型: 国际会议

会议名称: 9th International Conference on Solid-State and Integrated-Circuit Technology(第9届固态和集成电路国际会议)

会议地点: 北京

会议语种:英文

页码: 2329-2332

在线出版日期: 2008-10-20（万方平台首次上网日期，不代表论文的发表时间）