A High Utilization Rate Routing Algorithm for Modern FPGA
Different from older generation of FPGAs,routing resources of recent FPGAs are described by hierarchical General Routing Matrix (GRM). In this paper,we present a routing algorithm which utilizes routing resources more efficient for GRM based FPGAs. First,we build routing resource graph (RRG) by a bottom-up way,then we combine breadth-first search manner with A* directed by a certain proportion to enhance utilization rate of routing resources,and this routing algorithm has high-adaptability to latest FPGA routing architectures. The experiment result shows that the utilization rate of hex lines and bng lines has been raised by 6% and 9% respectively.
Ding Xie Jimmei Lai Jiarong Tong
ASIC & System State Key Laboratory,Fudan University,Shanghai 201203 PR.China
国际会议
9th International Conference on Solid-State and Integrated-Circuit Technology(第9届固态和集成电路国际会议)
北京
英文
2333-2336
2008-10-20（万方平台首次上网日期，不代表论文的发表时间）