Fast Substrate Noise Driven Floorplanning for Mized-Signal Circuits Considering Symmetry Constraints

摘要：

With the continuous increase of chip complexity and blocks density,the conventional substrate noise optimization tools which are based on some substrate noise models will consume a period of unbearable time. Further more,all the tools only aim at decreasing the total noise but ignore the specific constraints of analog parts such as symmetry constraint In this paper,we first prove the effectiveness of Block Preference Directed Graph (BPDG) to decrease both noise sum of all analog blocks and noise gradient on symmetrical blocks. Then we implement the concept of BPDG with Corner Block List (CBL),with which the noise estimation process can be finished in linear time. Finally,the experimental results prove that both the time and the quality of final placement can be greatly improved by our method.

作者: Jiayi Liu Sheqin Dong Xianlong Hong

作者单位: EDA Lab,Tsinghua University,Beijing 100084,P.R.China

会议类型: 国际会议

会议名称: 9th International Conference on Solid-State and Integrated-Circuit Technology(第9届固态和集成电路国际会议)

会议地点: 北京

会议语种:英文

页码: 2337-2340

在线出版日期: 2008-10-20（万方平台首次上网日期，不代表论文的发表时间）