Design of Multiphase Decimation Filter IP Core in Software Radio Receiver

摘要：

This thesis introduces the design of multiphase decimation filter IP core in software radio receiver in detail. This soft-core could automatically generate Verilog-HDL code with optimized-structure according to input parameters. The application of this core can decrease the design time and cost, and improve reliability; it can also be combined with the dynamic reconfiguration FPGA technology to realize the aim that real-time changing filter performance in order to satisfy the flexible demand of software radio application system.

关键词： Software Radio Multiphase Decimation Filter IP Soft-Core Dynamic Reconfiguration FPGA

作者: Donghai Yu Ningchen Wang Yijun Gui

作者单位: State Key Laboratory of Millimeter Waves, Southeast University Nanjing, 210096, China

会议类型: 国际会议

会议名称: The 4th International Conference on Wireless Communications, Networking and Mobile Computing(第四届IEEE无线通信、网络技术及移动计算国际会议)

会议地点: 大连

会议语种:英文

页码: 1-5

在线出版日期: 2008-10-12（万方平台首次上网日期，不代表论文的发表时间）