FPGA Design and Implementation of an Improved 32-bit Binary Logarithm Converter

摘要：

This paper presents an improved 32-bit binary logarithm converter, which is optimized according to the characteristics of Xilinx Virtex4 series FPGA. The implementation in FPGA denotes that our improved method not only costs less resources but also has much higher speed. Meanwhile a novel and simple error correction method is proposed. It reduces the converter error to only one half of the Metchells method. The analytical results of the approximation error are confirmed by numerical simulation results.

作者: Zhijun Li Jianping An Miao Yang Jing Yang

作者单位: Department of Electronic Engineering, Beijing Institute of Technology Beijing, 100081, P.R.China

会议类型: 国际会议

会议名称: The 4th International Conference on Wireless Communications, Networking and Mobile Computing(第四届IEEE无线通信、网络技术及移动计算国际会议)

会议地点: 大连

会议语种:英文

页码: 1-4

在线出版日期: 2008-10-12（万方平台首次上网日期，不代表论文的发表时间）