An Efficient MV Prediction VLSI Architecture for H.264 Video Decoder

摘要：

Variable block sizes, complex spatial motion vector prediction, particular skip and direct temporal MV prediction contribute to superior performance of H.264 standard. However, high irregularity of its MV prediction algorithm also makes efficient hardware implementation challenging. In this paper, an efficient VLSI architecture is proposed for irregular MV prediction implementation. Complex control logic is simplified by regularly lookuping control parameters in a predefined table. The parameters of the current MB and neighboring blocks are also initialized and updated regularly. Pipeline and parallelism are jointly employed in the proposed architecture to shorten the processing time and minimize hardware consumption. Moreover, highly regular architecture also simplifies the function verification considerably. Simulation results verify the effectiveness of the proposed design.

作者: HaiBing Yin DongPing Zhang XiuMin Wang ZheLei Xia

作者单位: Information Engineering Department, China Jiliang University Institute of Digital media, PekingUnive Information Engineering Department, China Jiliang University

会议类型: 国际会议

会议名称: 2008 International Conference on Audio，Language and Image Processing(2008国际声音、语言、图像过程大会)

会议地点: 镇江

会议语种:英文

页码: 423-428

在线出版日期: 2008-07-07（万方平台首次上网日期，不代表论文的发表时间）