Hardware Implementation of Transform and Quantization for AVS Encoder

摘要：

Multimedia applications need larger and larger bandwidth. The only way to face the demands is to provide better and faster video compression standard. Thus, A VS is created in China. To address the need for hardware acceleration of its computationally intensive parts, high throughput hardware architectures for fast computation of the 2-D Transform Quantization Inverse Quantization and Inverse Transform are presented in this paper. In addition, two high performance system architectures are presented. The proposed hardware architectures are incorporated into two different hardware systems implemented on a Virtex 4 Pro FPGA. Simulation results show that both two hardware system architectures that are incorporated proposed architectures could provide satisfactory performances.

作者: Leirui Wang Zhaoyang Zhang Guowei Teng Liquan Shen Xuli Shi

作者单位: Key Lab.Of Advanced Display and System Application, Ministry of Education, Shanghai Univ., Shanghai, 200072, China

会议类型: 国际会议

会议名称: 2008 International Conference on Audio，Language and Image Processing(2008国际声音、语言、图像过程大会)

会议地点: 镇江

会议语种:英文

页码: 843-847

在线出版日期: 2008-07-07（万方平台首次上网日期，不代表论文的发表时间）