Investigation into the Assembly Process of 0.3mm Wafer Level Chip Scale Package
Based on the speed at which other miniaturized components (0201s, 0.4mm CSPs, etc.) have moved into the manufacturing landscape, it is apparent that this trend will continue and that the next component challenge on the horizon will be 0.3 mm Chip Scale Packages (CSPs). This device will require arrays of mass imaged solder paste at pitches and volumes that only a few short years ago would have warranted a semiconductor classification. Suffice it to say, the 0.3mm CSP represents a major evolution within the SMT arena. When one considers the sub-7 second cycle times employed in surface-mount production versus the comparatively slow ball bumping cycles consistent with semiconductor processes, transitioning the 0.3 mm CSP device to standard SMT volumes and cycle times will be a monumental task. Other considerations include the thin, often uneven FR4 boards generally used in SMT versus the perfectly flat wafers and the standard working environments of a typical assembly operation versus the clean-room environments found in semiconductor packaging facilities. Even with all of these tremendous hurdles, though, 0.3 mm CSPs are coming and manufacturers need to be prepared. This paper will present results from research into the key influential elements of the deposition process. Process design factors such as solder paste, stencil design, stencil fabrication are fully investigated. In addition, the impact of typical production defects associated with the fabrication of stencils will be observed to ensure that the study presents real-world – as opposed to laboratory – process conditions.The deliverables from this paper will be clear and concise implementation solutions for surface mount engineers who will be required to assemble 0.3mm CSPs.
Clive Ashmore
Dek Printing Machines Weymouth,UK
国际会议
上海
英文
2008-03-17（万方平台首次上网日期，不代表论文的发表时间）