New Memory-Efficient Hardware Architecture of 2- D Dual-mode Lifting-Based Discrete Wavelet Transform for JPEG2000
This work presents new algorithms and hardware architectures to improve the critical issues of the 2-D dual-mode (supporting 5/3 lossless and 9/7 lossy coding) lifting-based discrete wavelet transform (LDWT). The proposed 2-D dualmode LDWT architecture has the advantages of low-transpose memory, low latency, and regular signal flow, which is suitable for VLSI implementation. The transpose memory requirement of the N×N 2-D 5/3 mode LDWT is 2N, and that of 2-D 9/7 mode LDWT is 4N. According to the comparison results, the proposed hardware architecture surpasses previous architectures in the aspects of lifting-based low-transpose memory size. It can be applied to real-time visual operations such as JPEG2000, MPEG-4 still texture object decoding, and wavelet-based scalable video coding.
lifting-based discrete wavelet transform (LDWT),interlaced read scan algorithm (IRSA) low-transpose memory 2-D 5/3 mode LDWT 2-D 9/7 mode LDWT.
Chih-Hsien Hsia Jen-Shiun Chiang
Dept.of Electrical Engineering Tamkang University Taiwan,ROC
国际会议
广州
英文
2008-11-19（万方平台首次上网日期，不代表论文的发表时间）