A Low-Phase-Noise Frequency Synthesizer for Single-Chip CMOS UHF RFID Reader

摘要：

A novel fraedonaI-N frequency synthesizer which is based on delta sigma modulator (DSM) and specialized for single-chip ultra-high frequency radio-frequency identification (UHF RFID) reader is proposedIn This paper. The fractional-N synthesizer is implementedIn0.181μm CMOS process. The phase noise of the fractionaI-N synthesizer is approximately -109 dBc/Hz and -129 dBc/Hz at 200 kHz and 1 MHz offset from 900 MHz operating frequency while drawing 9.6 mA from 1.8 V power supply. The synthesizer is evaluated by implementing it ina direct conversion RF front-end. The front-end features a noise figure of 3.5 dB and an input-referred third-order intercept point of 5 dBm.

作者: Runxi Zhang Yihao Chen Chunqi Shi Zongshen Lai

作者单位: IMCS,East China Normal University,Shanghai,China

会议类型: 国际会议

会议名称: 2008 International Conference on Microwave and Millimeter Wave Technology(2008国际微波毫米波技术会议)

会议地点: 南京

会议语种:英文

页码: 1477-1480

在线出版日期: 2008-04-21（万方平台首次上网日期，不代表论文的发表时间）