A 5GHz 0.18-μm CMOS technology PLL with a symmetry PFD
A fast-locking low-jitter phase-locked loop (PLL)withA simple phase-frequency detector has been proposed. The phase-frequency detector is composed of only two XOR gates. It can achieve performances of both low jitter and short locking time simultaneously. The voltage-controlled oscillator within the PLL consists of four-stage ring oscillators which are coupled to each other and oscillate with the same frequency and a phase shift of 45 degrees. The PLL is fabricated in a 0.18-pm CMOS technology. Measured phase noise of the PLL output at 500kHz offset from the 5GHz center frequency is -102.6dBc/Hz. The circuit exhibitsA capture range of 280MHz andA low rms jitter of 2.06ps. The power dissipation excluding the output buffers is only 21.6 mW at a 1.8-V supply.
Yingmei, Chen Zhigong, Wang Li, Zhang
Institute of RF&OE-ICs,Southeast University,Nanjing,210096,China
国际会议
2008 International Conference on Microwave and Millimeter Wave Technology(2008国际微波毫米波技术会议)
南京
英文
562-565
2008-04-21（万方平台首次上网日期，不代表论文的发表时间）